Procedure and circuit for detection of the information of a received signal

ABSTRACT

Two phase-shifted quadrature signals are formed from a reception signal modulated by frequency-shift keying. Instant values of one of the quadrature signals are taken at the instant when the other quadrature signal passes through zero and vice-versa. The readout values obtained during an interval of one data bit are alternatingly inverted in their polarity or left unchanged, so that a sequence of readout values of adapted polarity is formed. The values are algebraically added in an added during each of the bit intervals. The sign of the resultant sum determines the evaluated value of the received information symbol `0` or `1` and the amount of the sum is a measure of the quality of the evaluation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention concerns a procedure for detection of theinformation of a received signal, as well as an electric circuit forimplementing the procedure. Preferentially, the invention will serve toestimate a binary information item in a received signal modulated byfrequency shift-keying (FSK).

2. Related Art

Various circuits for the reception of signals modulated by frequencyshift-keying (FSK) are already known. The traditional incoherentcircuits accumulate the energy of the received signal in each case forone bit period on the two frequencies F₀ and F₁, which represent the twobinary symbols `0` and `1.` The frequency which, in each case, has thehigher signal energy, provides the estimation value of the correspondinginformation symbol. These classical receivercircuits are explicitelydescribed, e.g., by John M. Wozencraft and Irwin M. Jacobs in the bookPrinciples of Communicatons Engineering, John Wiley and Sons, New York,1965. These known circuits are theoretically optimal; however, in theirpractical application, they are very susceptible to non-idealcharacteristics of the oscillators and filters, as well as deviation ofbroadcast frequencies from their ideal values.

SUMMARY OF THE INVENTION

The problem for the present invention is to enable the detection of theinformation of a received signal in a relatively simple matter and withrelatively minimal energy utilization, even under non-ideal conditions,particularly if the received signal has a considerable portion ofundesirable interference overriding the useful signal representing theinformation, e.g., static and signal interference.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following description, the invention is explained in greaterdetail by reference to the attached drawings, purely as an example.

FIG. 1 shows schematically a circuit for detecting binary information ina received signal modulated by frequency shift-keying (FSK);

FIG. 2 is a diagram representing the manner of operation of the circuitaccording to FIG. 1, and shows various electrical signals which dependon time.

DETAILED DESCRIPTION

The circuit represented in FIG. 1 provides a signal input 20 for thepossibly preamplified high-frequency received signal U1 which ismodulated by frequency shift keying (FSK) between 2 frequencies f₀ andf₁. the signal input 20 is connected by means of wires 21 and 22 to theinput of an initial mixer 23 and input to a second mixer 24. Anoscillator 25 generates a sinusoidal oscillation with a constant centerfrequency of: ##EQU1## and is connected by means of a wire 26 with asecond input of the initial mixer 23, and by a wire 27 with aphase-displacement device 28. At the output of the phase-displacementdevice 28, there is a sinusoidal oscillation U3, which is phase-shiftedby 90° in relation to the sinusoidal oscillation U2, and has the samefrequency, f_(c). The oscillation U3 is passed by means of a wire 29 toa second input of the second mixer 24. The two mixers 23 and 24 generatemixed products U4 and U5, which are each passed by way of wires 30 and31, respectively, to an initial low-frequency pass filter 32, and asecond low-frequency pass filter 33, respectively. At the outputs of thetwo low-frequency pass filters 32 and 33 are twosinusoidally-progressing quadrature signals U6 and U7, which both havethe deviation frequency: ##EQU2## but which are phase-shifted by 90° inrelation to one another. The described transformation of the receivedsignal U1 to a low-frequency band in a single step is known as directconversion.

The first quadrature signal U6 is passed by means of a wire 34 to aninstantaneous value-sampler 35, which is controllable by an electricalsignal U8. The latter is generated by a crossover detector 36, anddelivered by way of a wire 37 to a control input of the sampler 35. Thesecond quadrature signal U7 is passed by way of a wire 38 to the inputof crossover detector 36. The sampler 35 and the crossover detector 36are made in such a way that at each crossover of the second quadraturesignal U7, a sampling of the instantaneous value of the first quadraturesignal U6 occurs. In a completely analogous manner, the secondquadrature signal U7 is passed by way of a wire 39 to a secondinstantaneous sampler 40 which is controllable by an electrical controlsignal U9. The latter is generated by a second crossover detector 41 andis passed by way of a wire 42 to a control input of the second sampler40. The first quadrature signal U6 is passed by way of a wire 42 to theinput of second crossover detector 41. The second sampler 40 and thesecond crossover detector 41 are made in such a way that at eachcrossover of the first quadrature signal U6, a sampling of theinstantaneous value of the second quadrature signal U7 occurs.

The sequence of samples U10 generated by the first sampler 35 is passedby way of a wire 43 to a controlled polarity inverter 44, and thesequence of scan values U11 generated by the second sampler 40 is passedby way of a wire 45 to a second controlled polarity inverter 46. Thefirst crossover detector 36 is furthermore made so that it generates acontrol signal U12 in each case when a second quadrature signal U7crosses a zero-point in a certain direction, e.g., from minus to plus.This control signal U12 is passed by way of a wire 47 to a control inputof the first polarity inverter 44. Similarly, the second crossoverdetector 41 is made so that it generates a control signal U13 in eachcase when the quadrature signal U6 crosses a zero-point in the oppositedirection, e.g., from plus to minus, and this control signal U13 ispassed by way of a wire 48 to a control input of the second polarityinverter 46. Accordingly, the control of the two polarity inverters 44and 46 occurs according to mutually opposite rules. At the outputs ofthe polarity inverters 44 and 46, sequences of samples U14 and U15,respectively, appear with adapted polarities, as is to be explainedbelow.

The outputs of the polarity inverters 44 and 46 are connected by meansof wires 49 and 50 with two inputs of an adder 51, which is controllableby means of a timing signal U16, and has two signal outputs 52 and 53.The adder 51 is in addition made so that during each period of timecontrolled by the timing signal U16, it algebraically adds the inputscan values U14 and U15, and then outputs an electrical signal U17 atthe signal exit 52 which corresponds to the digit sign of the sumobtained; and outputs at the signal exit 53 an electrical signal whichcorresponds to the amount of the sum. In order to generate the timingsignal U16 for controlling the adder 51, an oscillator 54 is presentwhose output is connected by way of a wire 55 with a control input ofthe adder 51. A synchronizer 56 is provided for the oscillator 54, theformer having two signal entries which are connected by way of wires 57and 58 with the outputs of the polarity inverters 44 and 46. Thesynchronizer 56 contains, for this purpose, a phase correction estimatorwhich is capable of comparing the phase of the oscillator 54 with thetime of the frequency shift keying of the received signal U1, and ofcorrecting towards zero any deviations which occur by means ofcorresponding effect on the oscillator 54. Preferentially, theoscillator 54 is a quartz oscillator whose oscillation period is set touniform time intervals, established from the emission side, between twopoints in time in which frequency shift keyings are possible.

The method of operation according to FIG. 1 of the circuit described,and the procedure for detecting the information of the received signalU1 that can be implemented with the circuit, are, e.g., essentially asfollows:

The received signal U1, which is modulated by frequency shift keying,has the frequency f₀ or f₁, depending on whether the received signalrepresents the information symbol `0` or `1.` Accordingly, the receivedsignal U1 has a binary data sequence. The time duration T of theindividual bit intervals is constant and established from the emissionside. Thus, T is the bit period. In FIG. 2, at the top, several bitintervals--i-1, i, i+1, i+2--of a binary information signal with thesymbol sequence `1`, `0`, `1`, `1`, as well as the section of thereceived signal U1 corresponding to this symbol sequence, arerepresented.

In the mixers 23 and 24, the received signal U1 is mixed with themedium-frequency signal U2 or U3, as applicable, which is generated bythe oscillator 25. The mixture products U4 and U5 thus produced have thedeviation frequency Δf=f₀ -f_(c) =f_(c) f₁, where: ##EQU3## is thefrequency of the sinusoidal oscillations generated by the oscillator 25.The higher mixture products with frequencies f₀ +f_(c) or f₁ +f_(c) aresuppressed by the low pass filters 32 and 33, so that the quadraturesignals U6 and U7 with the deviation frequency: ##EQU4## appear at theoutputs of the low pass filters. As already mentioned, the twoquadrature signals U6 and U7 are phase-shifted by 90° in relation to oneanother. If the received signal U1 in a bit interval has the frequencyf₀ representing the symbol `0,` the sinusoidal oscillation of the firstquadrature signal U6 moves on ahead of the sinusoidal oscillation of thesecond quadrature signal U7 by 90°. If, on the other hand, the receivedsignal U1 in a bit interval has the frequency f₁ which represents thesymbol `1`, the sinusoidal oscillation of the first quadrature signal U6follows the sinusoidal oscillation of the second quadrature signal U7 by90°. An ascertainment or estimate of the differing phase positions ofthe sinusoidal oscillations of the two quadrature signals U6 and U7 isaccordingly synonymous with an estimate of the information symbolcontained in the received signal U1. Knowledge of the phase positionthus unmistakably indicates the information symbol received in eachcase.

In order to clarify the above, the the two quadrature signals U6 and U7are represented in FIG. 2 in the bit intervals i and i+1. The change inthe different phase positions can be clearly seen by the transition fromthe information symbol `0` to the information symbol `1` in the instant(i+1)T. The graphic representation of the quadrature signals U6 and U7also shows that in reference to the instants i.T, (i+1)T and (i+2)T, ineach of which a frequency shift keying of the received signal U1 occursor may occur, can have any phase position, so that neither the zeropoints nor the maxima of one or the other quadrature signal coincideswith the instant named. This is represented graphically in FIG. 2 by thetime duration t_(s) at the beginning of the bit interval i.

In practice, undesirable interferences signals override the receivedsignal, for which reason the two quadrature signals U6 and U7 show notonly the sinusoidal oscillations indicated in FIG. 2, but, in additionthe interference signals, of some frequency or other, which areoverriding the sinusoidal oscillations, whereby the amplitudes of theinterference signals may under certain circumstances be greater than theamplitudes of the sinuosoidal oscillations. For the detection of theinformation of the received signal U1, it is necessary to recognize ineach bit interval the portion of the oscillations contained in thequadrature signals U6 and U7 which have the frequency Δf, which ishereinbelow called the useful signal portion.

If the useful signal portion in the quadrature signal U6 is known in thebit interval i, the optimum ML (maximum likelihood) estimation rule forthe i-th information symbol is as follows: ##EQU5## In this formula,U_(c) (t) indicates the quadrature signal U7 as a function of time, andcos (2πΔf(t-t_(s))-π/2) indicates the useful portion in the quadraturesignal U7 that is expected in a transmitted information symbol `0.` Tand t_(s) have the meanings already indicated. The letters S and H standfor `statistic` and `hypothesis,` respectively.

If S≧0, a transmitted information symbol `0` is assumed; otherwise, atransmitted information symbol `1` is assumed.

If this calculation is to be conducted with time-discrete values, e.g.,by means of an electronic calculator, the estimation rule is: ##EQU6##Where T_(a) means the sub-period or sampling period at which thequadrature signal U7 is sampled within one bit period T, which occurs Ntimes per bit period.

Thus, according to this estimation rule, the instantaneous value of abit period T of the quadrature signal U7 is sampled N times; the samplesobtained are weighted with fixed coefficients corresponding to thefunction values of the expected useful signal portion at a transmittedinformation symbol of `0,` and all N products which have thus beenformed are summed up. Everywhere where the amount of the expected usefulsignal portion is equal to 1, when the transmitted signal is `0,` thesamples are given a maximum weighting according to the amount. If, forthe estimation, samples at only these points are utilized, themultiplication of the weighting may be replaced by additions andsubtractions. Since only those samples which are most heavily weightedin the summation are used for this, the result of this procedure isclose to the optimum.

Due to the 90° phase displacement between the sinusoidal oscillations U2and U3, the useful signal portions of the two quadrature signals U6 andU7 in each case have their maximums and minimums where the useful signalportion of the other quadrature signal U7, or U6, respectively, crossesa zero-point. Instead of detecting the phase of the useful signal of oneof the quadrature signals U6 or U7, and thereafter estimating therelative phase position of the useful signal portion of the otherquadrature signal U7 or U6, respectively, the instants of thezero-passages of the one quadrature signal U6, or U7, respectively, maybe used for controlling the sampling of the other quadrature signal U7,or U6, respectively.

Accordingly, in the circuit according to FIG. 1, the instantaneous valueof the first quadrature signal U6 is sampled by means of the firstsampler 35, which is controlled by the crossover detector 36, wheneverthe second quadrature signal U7 passes through a zero-point. Conversely,the instantaneous value of the second quadrature signal U7 is sampled bymeans of the second sampler 40, which is controlled by the crossoverdetector 41, whenever the first quadrature signal U6 passes through azero-point. The sequences of samples U10 and U11, respectively, whichare obtained, are represented in FIG. 2. Recognizably, the samples havealternating polarities within a single bit-period.

By means of the controlled polarity inverters 44 and 46, the samples arein part inverted and in part not inverted. The criterion for whether thesample is to be inverted or left uninverted is the direction of thecross-over of the other quadrature signal. In the example according toFIG. 2, samples U10 of the first quadrature signal U6 are alwaysinverted whenever the second quadrature signal U7 crosses a zero pointfrom plus to minus; on the other hand, the samples of the secondquadrature signal U7 are always inverted whenever the first quadraturesignal U6 crosses a zero-point from minus to plus. Accordingly,sequences of samples U14 and U15 with adapted polarities are created atthe exit of the polarity inverters 44 and 46, as can be seen at thebottom of FIG. 2. It is recognizable that within the bit interval i,during which the information symbol `0` is transmitted, all adaptedsamples U14 and U15 have positive polarity, and within the bit intervali+1, during which the information symbol `1` is transmitted, all adaptedsamples U14 and U15 have negative polarity.

If the received signal U1, and hence also the two quadrature signals U6and U7, are not free of interference signals, the samples U14 and U15may indicate differing amounts, and the points in time of the crossoversof the quadrature signals may be irregularly shifted. Since, however,the sinusoidal oscillations have, in each case, the greatest increasesat their crossovers, and the sampling occurs at the flattest range ofthe useful signal portions, the samples obtained in the manner describedpermit a good approximation of the optimal estimation rule, even incases of a received signal burdened with static and interference.

In the adder 51, the samples U14 and U15 with adapted polarity valuesare algebraically added during each bit interval, after which anelectrical signal representing the preceding sign of the resulting sumappears at the signal output 52, and an electrical signal representingthe amount of the resulting sum appears at the signal output 53. Thepreceding sign of the resulting sum determines the esimated informationsymbol `0` or `1,` while the amount of the sum is a measure of thequality of the estimate made.

The control of the adder 51 occurs by means of the timer signal U16generated by the oscillator 54, which is synchronized with the bitperiod T. The polarity exchange of the samples U14 and U15 between thesequential bit intervals is used for the synchronization in each case.The samples U14 and U15 are passed to the synchronizer 56 by way of thewires 57 and 58, which compares the instants of the polarity exchange ofthe samples U14 and U15 with the points in time of the flanks of thetiming signal U16, which control the adder 51, and corrects toward zeroany deviations which may occur by means of corresponding influence ofthe phase of the timing signal U16. In this way the chronologicalcoincidence, to a sufficient degree of exactness, of the flanks of thetiming signal U16 with the instants i.T, (i+1)T, (i+2)T, etc., betweenthe sequential bit intervals, is achieved.

For the expert it is clear that other measures of circuit technologywould be possible for generating the timing signal U16 which controlsthe adder 51. It would also be conceivable for the timing signal U16 tobe transferred from the transmitter, either on a separate controlchannel, or overriding the received signal U1. Since, however, thepresent invention has the goal of detecting the information of thereceived signal U1 even with poor transmission quality, it is to beassumed that the transmission of the timing signal U16 from thetransmitter might occur with insufficient quality, and that theestimation of the information of the receiver signal might be negativelyinfluenced. Therefore, the generation of the timing signal U16 at thelocation of the receiver would be preferred.

In a simplified alternative to the described circuit according to FIG. 1it is possible to dispense with the second sampler 40, the secondcrossover detector 41 and the second polarity inverter 46, and simply togenerate samples U14 from the first quadrature signal U6, and to addthem in the adder 51. Conversely, the sampler 35, the crossover detector36 and the polarity inverter 44 may be omitted, so that then, onlysamples U15 from the second quadrature signal U7 are formed in each caseat the crossovers through zero by the first quadrature signal U6, andare added in the adder 51. In each of these simplified cases, however,the quality of the estimate of the information of the received signal U1achieved is of a lesser quality than in the example according to FIG. 1with cross-control of the sampling of both quadrature signals U6 and U7,because in the latter case, a part of the information loss, which mayoccur due to the non-ideal character of the point in time of the sampleof only one of the quadrature signals, is compensated for.

Finally, it should be noted that the center frequency f_(c) of thesinusoidal oscillation U2 generated by the oscillator 25 may be locatedin any frequency range whatsoever; however, the relationship of thedeviation frequency: ##EQU7## in Hertz to the data rate R in bits persecond need only fulfill the condition: ##EQU8##

I claim:
 1. Method for detecting binary information in a received signal, comprising initially demodulating said received signal into a first quadrature signal and a second quadrature signal which is phase shifted by 90 degrees, converting each of said first and second quadrature signals into a sequence of samples corresponding to the amplitude and polarity of the associated quadrature signal at instant of the sampling, whereby the instant of the sampling is controlled dependent on the crossover of the other quadrature signal in each case; inverting or non-inverting the polarity of the samples obtained, dependent upon the directions of the crossovers of the other quadrature signal in each case; whereby the inversion of samples of the first quadrature signal and the inversion of the samples of the second quadrature signal occurs, in each case, at opposite directions of the crossovers of the second quadrature signal and the first quadrature signal, to generate samples with adapted polarities within each individual information bit interval of the received signal from both quadrature signals; summing all samples with adapted polarities within each individual information bit interval of the received signal, and evaluating the preceding sign of the resulting sum as an estimate of the received binary information symbol.
 2. Method according to claim 1, wherein the amount of the resulting sum of all samples with adapted polarities within an information-bit interval of the received signal is evaluated as the standard of quality of the estimate of the received binary information symbol.
 3. Electrical circuit for detecting binary information in a received signal, comprising circuit elements for demodulating a received signal into a first quadrature signal and a second quadrature signal which is phase-shifted by 90 degrees from said first quadrature signal, conversion means for converting each of the quadrature signals into a sequence of samples, corresponding to the amplitude and polarity of the quadrature signal existing at the instant of the sampling; means for controlling the instants of the sampling, dependent on the crossover through zero of the other quadrature signal in each case; means for inverting a portion of the samples obtained dependent on the directions of the crossovers through zero of the other quadrature signal in each case, such that the inversion of the samples of the first quadrature signal occurs, in each case, at oppositie directions of the crossovers through zero of the second quadrature signal and the first quadrature signal, to generate within each individual information bit interval of the received signal, samples with adapted polarities, from both quadrature signals; means for adding all samples with adapted polarities within each individual bit interval algebraicially; and means to generate an output signal which signals have the preceding sign of each resulting sum, which represents an estimate of the received binary information symbol.
 4. Circuit according to claim 3, wherein the means for converting each quadrature signal into a sequence of samples are instantaneous value samples for sampling the first and second quadrature signals, respectively, and means for controlling the instants of the sampling are two crossover detectors for ascertaining the crossovers through zero of the first and second quadrature signals, respectively, whereby the control signals generated by the crossovers of the first quadrature signal are passed to the instantaneous value sampler for the second quadrature signal, to control the instantaneous value sampler, and the control signals generated by the crossovers of the second quadrature signal are passed to the instantaneous value sampler for the first quadrature signal, to control the latter-mentioned instantaneous value sampler.
 5. Circuit according to claim 4, wherein the means for inverting a portion of the samples include two polarity inverters controllable by control signals, for the samples of the first quadrature signal, and the samples of the second quadrature signal, respectively; and the crossover detectors generate a control singal for the polarity inverters, dependent upon the direction of the crossovers through zero of the second and first quadrature signals, respectively.
 6. Circuit according to claim 3, wherein the means for algebraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.
 7. Circuit according to claim 3, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.
 8. Circuit according to claim 4, wherein the means for algegraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.
 9. Circuit according to claim 5, wherein the means for algebraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.
 10. Circuit according to claim 4, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.
 11. Circuit according to claim 5, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.
 12. Circuit according to claim 6, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.
 13. Circuit according to claim 8, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.
 14. Circuit according to claim 9, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol. 